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MCF5249 embedded microprocessor and its application

MCF5249 embedded microprocessor and its application
Abstract: This paper introduces the company's embedded microprocessor MCF5249 MOTOROLA principle, characteristics, and pin functions, indicating that the processor-based embedded operating system and network cameras UCLINUX structure, given the camera with the MCF5249 when designing the network The distribution of resources and circuit design considerations.
Key words: MCF5249; embedded microprocessor; JPEG
1 Overview
MCF5249 is the motorola has introduced 32-bit embedded microprocessor, the device to ColdFire 32 位 microprocessor-based architecture, and with 96kB of on-chip SRAM, 8kB instruction cache, two independent UART and 16-bit timer and a PLL clock, and also with the software monitors the clock, GPIO lines, two I2C interfaces,[link widoczny dla zalogowanych], QSPI port, 4-channel DMA and SDRAM controller, a non-adhesive. In addition, the device also integrates a 12-bit DAC and an enhanced multiply-accumulate  EMAC  unit, can be used to provide audio and other applications fast computing and signal processing DSP functions required. MCF5249 maximum operating frequency of 140MHz, the performance of up to 125Dhrystone 2.1 MIPS, while the power consumption per MHz of only 1.3mW. Which can be used in audio equipment, imaging, biometric and industrial control and other fields. 2 Pin Description and Features
V2 ColdFire MCF5249 embedded processor core, 96kB static SRAM, 8kB instruction cache, EMAC enhanced multiply-accumulate units, two independent UART  UARTs , 2 independent 16-bit timer, two separate I2C interface, and four 16-bit width of the channel SDRAM controller module also integrates other MCF5249 PLL and software watchdog  Software watchdog , digital audio transmission and receiving port (in accordance with IEC958 audio protocol) and the IDE and SmartMedia Interface and so on. Figure 1 shows the block diagram of the main function of MCF5249.
MCF5249 can support CD-ROM and CD-ROM XA block coding and decoding functions, and selected with 4 programmable background real-time processing Debug module. Figure 1 MCF5249 chip core voltage is 1.8V, I / O voltage is 3.3V, with 160 feet MAPBGA (140MHz maximum frequency) and 144 feet QFP (120MHz maximum frequency) in two packages. 160 feet 144 feet adds more than MCF5249 QSPI CS1 pin functions.
2.1 with MCF5249 a network of cameras
These features are based on MCF5249, the author designed a captured image can be embedded real-time network transmission of the camera system. Shown in Figure 3  it by the image sensor, frame memory, network controller, keyboard, display modules and other components. One image sensor uses the company's OV9620 OMNIVISION CMOS image sensor resolution. The sensor has a resolution of 1280 × 1024 and 1024 levels of color information. The maximum recording speed of up to fifteen per second. OV9620 the control port and the I2C port directly connected to the MCF5249. To make the output image data easily connected with the frame memory, the author designed the high eight bits of data only. ISSI's frame memory using 18Mbit memory IS61LPD102418A. The memory data read rate of 7ns, and control is simple, easy to use. Set memory is due to the rate of pixels does not match with the MCF5249 rate, and with its role from the cache. Network controllers use the company's DM9000 Fast Ethernet DAVICOM control processor, the processor is equipped with standard 10M Ethernet interface, including MAC and PHY. Ethernet physical layer interface protocol. Since the data received in the form sometimes in a burst, and therefore, DM9000 receive buffer is also integrated so that data can receive data into the buffer, and then the data link layer taken directly from the buffer take data. Link layer typically includes the operating system device drivers and the corresponding computer network interface card, which together deal with the details of the physical interface data cable, its buffer can be used to temporarily store the frame to be sent or received. MCF5249 supplemented needed in the use of 4M × 16-bit data width of SDRAM and 4MB on-line can be erased FLASH MX29LV160BTC.
The system is working, first through the FLASH automatically load the operating system, then the I2C interface, system control MCF5249 to control the exposure and an image sensor to write SRAM. After collection, MCF5249 read through the GPIO port pixel data, and through the internal embedded JPEG image compression coding module to convert it into easy-to-network transmission of low data volume image data stream, and then output to the DM9000 network controller, the last transmission to the network .
For different requirements, can be divided into the camera's image resolution 320 × 240,640 × 480,1024 × 769 three levels, corresponding to different levels of resolution, image processing speed were 15fps (frame per second), 10fps, 3fps . Figure 2 shows the overall framework of the system. One of the display module 128 × 64 with 6963 series of LCD, mainly used to display the system clock, system status, and the card ID numbers. 4 Conclusion
In designing the network using MCF5249 image transmission system, should also note the following:
(1) a reasonable level ground and power isolation
Recommended as a more complete formation of a PLANE, if there are multiple The power plane should be similar. In addition, it should be noted that some low-noise circuitry and high power supply noise isolation circuit part or filtering.
(2) a reasonable arrangement of decoupling capacitors
In the power line side, all digital chip power pins are located generally near the appropriate decoupling capacitors. Should be designed so that the core board, in isolation, but also in all the input and output ports using the appropriate buffer.